Until now, our coverage of E3 is focused on two major announcements made by AMD around its future processor and GPU products. But the company also gave some other interesting presentations, including one on the evolution of Socket AM4.
Some technologies attract more attention than others. Nobody blinks at a deep dive of 10 or 20 slides in processor and GPU architectures, but we rarely talk about sockets or motherboard design – even though these are essential bases of the products we use. Without Socket AM4, a Ryzen processor it's just expensive sand. And as AMD said, there is an unprecedented story about how AM4 "evolves from a monolithic die with 4x28nm cores (Bristol Ridge) to 16-core mixed process chiplets".
As Moore's law slowed down, manufacturers turned to other methods to achieve the desired improvements from one generation to the next. Rather than rely on a net reduction of nodes to improve performance, they turned to packaging to earn new winnings. The AMD Fury X family of graphics processors, which began with the use of HBM, is a good example of how changing the package significantly reduces power consumption (the power of the memory subsystem in this case) while providing significant gains. Switching to smart cards is one of the ways businesses are working to solve this problem – but smart machines must always be connected together in a common socket standard.
AMD has laid the groundwork for its modular approach to chiplets with the first generation of Ryzen. Although it does not have an input / output matrix, the idea of building CPUs in their own discrete packages and connecting them to a common structure was still a step towards the increased modularity of chiplets. today.
A major challenge for AMD is to maintain pinout compatibility by switching from a 28-core 28-core monolithic system to a 14- and 7-nm mixed-core silicon system deployed on the same enclosure. Keep in mind, there is no way to change which pins bear what dates. Improvements can be made to the socket, but a change in socket design breaks compatibility with earlier versions.
AMD has reduced its pitch from 150 to 130 um to 7 nm Ryzen, despite the difficulties that this represented. There are only two vendors building this type of solution at the moment. To effectively make this transition, AMD had traditional lead-free protuberances and adopted so-called copper pillars, with a welding cap. This significantly reduces the height of the bumps.
The 12nm input / output chip would have used the default solder bumps, but the 7nm chips use copper posts for higher density. I / O should also be equipped with this solution to allow a common interface. New materials and interfaces were also needed for PCI Express 4.0 routing – AMD chose for the first time to use low loss materials and ranked its own work in this area as follows: "Take bets that have paid off ".
The routing scheme of the underlying chip. You can see the two chiplets at the top of the matrix and the wire traces that connect them to the I / O matrix. The four rectangular blocks of each CCX probably correspond to the L3 cache.
These enhancements are the first phase of chiplet and chiplet designs. The adoption of chiplets is still a very new phenomenon in the semiconductor industry. One of the reasons why we have not used them more widely, for example, is that there is no common interface or standard for chiplet designs. It's here that AMD and Intel have one advantage: both companies have experience in building dies to connect components and extensive IP portfolios to provide the necessary function blocks . We will see more and more companies experimenting with these methods over time and the emergence of new standards. Long-term chiplets could theoretically be used to attach different IP blocks, each built with different materials or on different process nodes.
In this case, the AMD chiplets are built on 7nm, the chipset on 14nm and the I / O interface section that actually manages the use of E / S uses 12 nm – which is actually optimized at 14 nm with design rules and modified libraries. (AMD has generally indicated that the chiplets measured 7 nm and 14 nm I / Os, but the company gave us a little more depth during its deep E3 dives).
AMD has not said anything about the expected life of AM4 or the fact that it would switch to AM5 after 2020. The company has reaffirmed that it intends to support AM4 socket "until 2020" but she did not say anything later. DDR5 Chipset – and AMD might well choose to introduce the AM5 Socket to take advantage of the need for routing and circuitry to support the new DRAM. This is a hypothesis, however, and the company has made no announcement.